RISC-V Architecture and Security Applications
Normal 0 21 false false false EN-US AR-SA Do you want to take full advantage of an open processor platform for your security applications? This 1-day masterclass explains the basics of the RISC-V architecture in a self-contained fashion and will present examples of its use for security applications.
The rise of RISC-V brought new opportunities for designers and engineers that need security. RISC-V can, in fact, be modified and extended to provide advanced security features or to accelerate specific cryptographic algorithms. In this masterclass, after an introduction to the fundamentals of the RISC-V architecture and a demonstration of a tool chain to use it, you will learn the most common attacks that are targeting the platform and the main mechanisms to counteract these threats. You will also familiarize yourself with the concept of instruction set extension and you will learn how it can be used to enhance the security functionalities of RISC-V.
More in detail, this masterclass will provide:
An introduction to the RISC-V architecture
An example of the RISC-V toolchain
Attacks on RISC-V
Protections on RISC-V
Instruction Set Extension for security in RISC-V
A quick highlight of some research activities in the domain of RISC-V security
After this masterclass you will:
Date: Thursday 22 June 2023, 09:00 - 17:00
Price: € 995,- (UvA alumni get a 10% discount. Fees are VAT-exempt)
Location: Lab42, Science Park 900, Amsterdam
Lecturer: Dr. Francesco Regazzoni
Visit our website to sign up or request a brochure with more information!
This masterclass is part of a series of three different hardware security masterclasses we offer. The other two masterclasses are:
